VLSI Architecture of High PerformanceTurbo Decoder for Wireless Sensor Networks

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

article

J.M.Mathana¹  S.Gunasekar²  S.Jagadish¹  R.Karthik¹ 

[1] Dept. of ECE, S.A Engineering College;Dept. of ECE, S.A. Engineering College

关键词: BMU;    SMU;    LCU;    ACS;    SISO.;   

来源: Research & Reviews

【 摘 要 】

The sensor nodes of a wireless sensor network (WSN) are typically required to maintain sporadic but reliable data transmissions for extended periods of time. However, in applications the sensor nodes have to be small, preventing the use of bulky batteries. The outstanding forward error correction capabilities of turbo codes made them part of many today’s communications standards. And also turbo codes have recently been considered for energyconstrained wireless communication applications, since they facilitate low transmission energy consumption. In this paper, a new low complexity ACS (add compare and select) architecture is introduced in the proposeddesign.The proposed turbo decoder is based on the LUT-Log-BCJR architecture.Entire decoder architecture is coded using Verilog HDL and it is synthesized using Xilinx EDA with Spartan 3E FPGA.

【 授权许可】

Unknown