Fault Tolerance Technique for DynamicallyReconfigurable Processor

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

article

Julia Mathew¹  R.Dhayabarani² 

[1] Department of Electronics and communication Engineering, V.S.B Engineering College;Department of Electronics and Communication Engineering, V.S.B Engineering College

关键词: Roll forward error recovery;    Fault Tolerance;    Partial Reconfiguration;    Lockstep scheme;    Triple modular redundancy.;   

来源: Research & Reviews

【 摘 要 】

This paper proposes a new technique to detect and eliminates temporary faults on FPGA systems. Soft core processors which can alleviate radiation induced failures is implemented on Virtex-5 FPGA’s. This Fault tolerant technique is implemented using TMR .It recovers from configuration upsets through partial reconfiguration combined with roll-forward recovery .The lockstep scheme used here eliminates configuration upsets without interrupting normal functioning. Main Significance includes less time overhead and reduced hardware usage. Fault injection Experiments are used for the validation process.

【 授权许可】

Unknown