Design of Gating Pulse Generation on FPGAusing CORDIC Algorithm for CascadedMulti- Level Inverter

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

article

ArunKumar.M¹  Gowdra Vinay Kumar¹  Sanjay Lakshminarayanan² 

[1] Dept. of ECE, EPCET;Dept. of EEE, MSRIT

关键词: Cascaded multilevel inverter;    CORDIC;    Verilog;    MATLAB/SIMULINK;    Gating pulses.;   

来源: Research & Reviews

【 摘 要 】

In this paper, FPGA based gate triggering pulses for five-level Cascaded Multilevel Inverter is designed. CORDIC algorithm is implemented on FPGA which is used for calculating different sine values. These sine values are used for generating gate pulses of five-level cascaded multilevel inverter. MATLAB/SIMULINK software was used for simulation and verification of proposed method.Gating signals are generated using FPGA Spartan-2 processor. The processor is designed using Verilog HDL using a structured coding method, simulated using Model Sim simulator and implemented using Xilinx 7.3FPGA synthesis Tool. The gating pulses are analysed and verified ,and compared with the actual pulses obtained from MATLAB/SIMULINK.

【 授权许可】

Unknown