Test Pattern Generator (TPG) for Low PowerLogic Built In Self Test (BIST )

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

article

Sabir Hussain¹  K Padma Priya² 

[1] Dept of ECE, MJ college of Engineering and Technology, Osmania University;Dept of ECE, University College of Engineering JNTUK

关键词: Low power;    Test Pattern Generation;    Linear Feedback Shift Register;    Logic Built in Self Test;   

来源: Research & Reviews

【 摘 要 】

This research article proposed a logic BIST using linear feedback shift register (LFSR) to generate low power test patterns; It reduced the number of transitions at the input of the circuit-under-test using bit swapping technique. The designed architecture is programmed using Verilog HDL and simulated using CADENCE EDA Tool of 180 nm technology and also proposed design gives better performance in term of power dissipation as compared to standard LFSR.

【 授权许可】

Unknown