DDRSHARP: A Fast and Extensible DRAM Simulator

Journal of computer sciences

article

Mohammed Ismail¹  Tesfamichael Gebregziabher Gebrehiwot²  Fitsum Assamnew Andargie² 

[1] Department of Electronics and Communication Engineering, Sasi Institute of Technology and Engineering;School of Electrical and Computer Engineering, Addis Ababa Institute of Technology

关键词: DRAM;    CPU;    Simulation;    Modeling;   

DOI  :  10.3844/jcssp.2023.836.846

学科分类：计算机科学（综合）

来源: Science Publications

【 摘 要 】

Dynamic Random-Access Memory (DRAM) is a crucial component of modern computing systems and there exist a variety of DRAM standards. The variance in DRAM architecture calls for an extensible simulator to accommodate current and future DRAM standards. Moreover, as every researcher may not be an expert in programming, choosing an easier programming language to construct a simulator would reduce the efforts of a researcher who seeks to reuse/modify existing code to meet the demands of his/her work. Performance bottleneck is another challenge of cycle-accurate simulators; some researchers even suggest statistical modeling to achieve higher speed by sacrificing accuracy. We present DDRSHARP, a cycle-accurate DRAM simulator written entirely in C#. It provides simplified configuration and evaluation of different DRAM standards. It includes both the performance and power/energy models of DRAM. In order to improve the performance of DDRSHARP, we skipped infeasible iterations on queued requests, minimized the number of branch instructions, saved repetitive calculations for later use, and minimized code execution paths. Since our simulator is constructed using C# and the garbage collector consumes a big amount of CPU time, we worked on minimizing heap allocation of immutable objects such as strings. Our approach has enabled more than 1.8 times speedup in performance compared to contemporary simulators.

【 授权许可】

CC BY