Design of Efficient Phase Locked Loop for Low Power Applications

Engineering Proceedings

article

Jagupilla Lakshmi Prasanna¹  Chella Santhosh¹  Mokkapati Ravi Kumar¹  Chandra Keerthi Pothina¹  Ngangbam Phalguni Singh¹ 

[1] Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation

关键词: Phase Locked Loop (PLL);    Phase Frequency Detector/Charge Pump (PFD/CP);    Low Pass Filter (LPF);    Current Starved Voltage-Controlled Oscillator (CSVCO);    Analog Digital Environment (ADE);   

DOI  :  10.3390/HMAM2-14157

来源: mdpi

【 摘 要 】

The phase-locked loop is a technique that has contributed significantly to technological advancements in many applications in the fast-evolving digital era. In this paper, a Phase Locked Loop (PLL) is designed using 90 nm CMOS technology node with 1.8 V supply voltage. It features a PLL design with minimum power consumption of 194.26 µW with better transient analysis and DC analysis in an analog-to-digital environment. The proposed PLL design provides the best solution for many applications where a PLL is required with high performance but has to be accommodated in less area and low power consumption than state-of-the-art methods. This PLL not only works at high speed but also makes whole system work at low power in a very effective manner, which suits the present digital electronics circuits.

【 授权许可】

Unknown