A Novel FPGA Implementation of the NAND-PUF with Minimal Resource Usage and High Reliability

Cryptography

article

Riccardo Della Sala¹  Giuseppe Scotti¹ 

[1] Department of Information, Electronics and Communication Engineering ,(DIET), Sapienza University of Rome

关键词: hardware security;    Field Programmable Gate Array (FPGA);    IoT;    Physical Unclonable Function (PUF);    secure hardware design;   

DOI  :  10.3390/cryptography7020018

学科分类：社会科学、人文和艺术（综合）

来源: mdpi

【 摘 要 】

In this work we propose a novel implementation on recent Xilinx FPGA platforms of a PUF architecture based on the NAND SR-latch (referred to as NAND-PUF in the following) which achieves an extremely low resource usage with very good overall performance. More specifically, a 4 bit NAND-PUF macro has been designed referring to the Artix-7 platform occupying only 2 slices. The optimum excitation sequence has been determined by analysing the reliability versus the excitation time of the PUF cells under supply voltage variations. A 128 bit NAND-PUF has been tested on 16 FPGA boards under supply voltage and temperature variations and measured performances have been compared against state-of-the-art PUFs from the literature. The comparison has shown that the proposed PUF implementation exhibits the best reliability performance while occupying the minimum FPGA resource usage achieved in the PUF literature.

【 授权许可】

CC BY