Investigation of endurance degradation for 3-D charge trap NAND flash memory with bandgap-engineered tunneling oxide

IEICE Electronics Express

article

Jongwoo Kim¹  Hyungjun Jo¹  Yonggyu Cho²  Hyunyoung Shim²  Jaesung Sim²  Hyungcheol Shin¹ 

[1] Inter-University Semiconductor Research Center ,(ISRC) and School of Electrical Engineering and Computer Science, Seoul National University;NAND Tech. Development Division, SK hynix Inc.

关键词: 3D NAND flash;    program/erase cycling stress;    endurance degradation;    mid-gap voltage;    hole tunneling current;    current fitting;   

DOI  :  10.1587/elex.19.20220465

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

In 3-D charge trap (CT) NAND flash memory, program/erase (P/E) cycling tests are performed, and the degradation of cell characteristics is investigated. The mechanism of mid-gap voltage (Vmg) shift difference between erased state and programmed state is presented and it is verified by technology computer-aided design (TCAD) simulation configured identically to the real device. TCAD simulation also makes it possible to extract the trap density through the current fitting. Generation of interface traps (Nit) and bulk traps in the tunneling oxide (Not) has the form of a power-law of the number of P/E cycles. Furthermore, it is experimentally found that the degradation of cell characteristics is mainly caused by hole tunneling current from the poly-silicon channel during erase operation.

【 授权许可】

CC BY