CASSANN-v2: A high-performance CNN accelerator architecture with on-chip memory self-adaptive tuning

IEICE Electronics Express

article

Feng Liu¹  Ruixiu Qiao¹  Gang Chen¹  Guoliang Gong¹  Huaxiang Lu¹ 

[1] Institute of Semiconductors, Chinese Academy of Sciences;University of Chinese Academy of Sciences;Semiconductor Neural Network Intelligent Perception and Computing Technology Beijing Key Laboratory;Materials and Optoelectronics Research Center, University of Chinese Academy of Sciences;College of Microelectronics, University of Chinese Academy of Sciences

关键词: SoC design;    convolutional neural network (CNN) accelerator;    high-performance accelerator;    architecture optimization;   

DOI  :  10.1587/elex.19.20220124

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

This work proposes a high-performance reconfigurable CNN accelerator architecture, called CASSANN-v2, which can achieve 1TOPS peak performance at 1GHz. CASSANN-v2 provides the function of on-chip SRAM memory real-time adaptive tuning by parameter configuration to reduce the intermediate output data transmission to further exploit the acceleration performance. The system simulation results show that CASSANN-v2 exhibits excellent performance on VGG-16 and ResNet-18 inference, with a throughput of 1009.54GOPS and 923.24GOPS at 1GHz, which achieved 98.59% and 90.20% average processing element utilization, respectively. Compared with state-of-the-art accelerator works, CASSANN-v2 improves the resource utilization by 2.02× in VGG-16 and 2.35× in ResNet-18.

【 授权许可】

CC BY