Exploiting bit-level write patterns to reduce energy consumption in hybrid cache architecture

IEICE Electronics Express

article

Juhee Choi¹  Heemin Park² 

[1] Dept. of Smart Information Communication Engineering, Sangmyung University;Dept. of Software, Sangmyung University

关键词: non-volatile memory;    STT-RAM;    energy saving techniques;    hybrid cache architecture;   

DOI  :  10.1587/elex.18.20210327

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

A hybrid cache architecture (HCA) is introduced to alleviate the drawbacks of non-volatile memory (NVM) technologies. Although researchers have offered meaningful ways to conserve energy, little attention has been paid to focus on write counts that are non-uniformly spread over a cache line. We propose a novel HCA to reduce the NVM write counts by exploiting bit-level write patterns. The data array is refined to separately store bits in the cache line to the NVM region and the SRAM region. As a result, 20.1% of energy is saved over prior works.

【 授权许可】

CC BY