Sparse BD-Net: A Multiplication-less DNN with Sparse Binarized Depth-wise Separable Convolution

ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS

Article

He, Zhezhi¹  Yang, Li¹  Angizi, Shaahin²  Rakin, Adnan Siraj¹  Fan, Deliang¹ 

[1] Arizona State Univ, Sch Elect Comp & Energy Engn, 650 E Tyler Mall, Tempe, AZ 85287 USA.;Univ Cent Florida, Dept ECE, 4328 Scorpius St, Orlando, FL 32816 USA.

关键词: Deep neural network;    model compression;    in-memory computing;   

DOI  :  10.1145/3369391

来源: SCIE

【 摘 要 】

In this work, we propose a multiplication-less binarized depthwise-separable convolution neural network, called BD-Net. BD-Net is designed to use binarized depthwise separable convolution block as the drop-in replacement of conventional spatial-convolution in deep convolution neural network (DNN). In BD-Net, the computation-expensive convolution operations (i.e., Multiplication and Accumulation) are converted into energy-efficient Addition/Subtraction operations. For further compressing the model size while maintaining the dominant computation in addition/subtraction, we propose a brand-new sparse binarization method with a hardware-oriented structured sparsity pattern. To successfully train such sparse BD-Net, we propose and leverage two techniques: (1) a modified group-lasso regularization whose group size is identical to the capacity of basic computing core in accelerator and (2) a weight penalty clipping technique to solve the disharmony issue between weight binarization and lasso regularization. The experiment results show that the proposed sparse BD-Net can achieve comparable or even better inference accuracy, in comparison to the full precision CNN baseline. Beyond that, a BD-Net customized process-in-memory accelerator is designed using SOT-MRAM, which owns characteristics of high channel expansion flexibility and computation parallelism. Through the detailed analysis from both software and hardware perspectives, we provide an intuitive design guidance for software/hardware co-design of DNN acceleration on mobile embedded systems. Note that this journal submission is the extended version of our previous published paper in ISVLSI 2018 [24].

【 授权许可】

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