A Novel Low-Power Synchronous Preamble Data Line Chip Design for Oscillator Control Interface

Electronics

Wei-Yuan Chiang¹  Chiung-An Chen¹  Ming-Yi Lin²  Shih-Lun Chen³  Min-Chun Tuan³  Tsun-Kuang Chi³  PatriciaAngela R. Abu⁴  Liang-Hung Wang⁵ 

[1] Department of Electrical Engineering, Ming Chi University of Technology, New Taipei City 301, Taiwan;Department of Electrical Engineering, National United University, Miaoli 36003, Taiwan;Department of Electronic Engineering, Chung Yuan Christian University, Chung Li City 320, Taiwan;Department of Information Systems and Computer Science, Ateneo de Manila University, Quezon City 1108, Philippines;Department of Microelectronics, College of Physics and Information Engineering, Fuzhou University, Fuzhou 350108, China;

关键词: SPI;    digital signal process;    communication protocols;    CMOS digital integrated circuit;    field-programmable gate array (FPGA);    electronic device measurement and very-large-scale integration (VLSI);   

DOI  :  10.3390/electronics9091509

来源: DOAJ

【 摘 要 】

In this paper, a novel low-power synchronous preamble data line protocol chip design for serial communication is proposed. The serial communication only uses two wires, chip select (CS) and secure digital (SD), to transmit and receive data between two devices. The proposed protocol aims to use a fewer number of wires for the interface, therefore reducing the complexity as well as the area of the chip design. Moreover, it increases the efficiency through a synchronous serial communication-controlled oscillator. The low-power synchronous preamble data line protocol design was successfully verified using a field-programmable gate array (FPGA) as a master device and a real chip as a slave device. The signals are checked through the use of a logic analyzer. The realized low-power synchronous preamble data line protocol chip design has a gate count of only 5.07 K gates, a low power dissipation of 12 mW, and a chip area of 453,260 μm² using the Taiwan semiconductor manufacturing company (TSMC) 0.18 μm CMOS process. Compared with the three-wire serial peripheral interface (SPI) protocol, the proposed design has the advantages of having a lower cost and a lower power consumption.

【 授权许可】

Unknown