A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

Electronics

Yumei Zhou¹  Shi Zuo¹  Jianzhong Zhao¹ 

[1] Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China;

关键词: DCO;    DCC;    ultra low power;   

DOI  :  10.3390/electronics10070805

来源: DOAJ

【 摘 要 】

This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μ$\mathsf{\mu }$W at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.

【 授权许可】

Unknown