Transverse Scaling of Schottky Barrier Charge-Trapping Cells for Energy-Efficient Applications

Crystals

Yu-Hsuan Chen¹  Jr-Jie Tsai¹  Chun-Hsing Shih¹  Hung-Jin Teng¹  NguyenDang Chien²  Chenhsin Lien³ 

[1] Department of Electrical Engineering, National Chi Nan University, Nantou 54561, Taiwan;Faculty of Physics & Nuclear Engineering, Dalat University, Lam Dong 670000, Vietnam;Institute of Electronics Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan;

关键词: Schottky barrier;    source-side injection;    charge-trapping memory;    energy-efficient;    non-planar double-gate;    high-k dielectrics;   

DOI  :  10.3390/cryst10111036

来源: DOAJ

【 摘 要 】

This work numerically elucidates the effects of transverse scaling on Schottky barrier charge-trapping cells for energy-efficient applications. Together with the scaled gate structures and charge-trapping dielectrics, variations in bias conditions on source-side injection are considered for properly operating Schottky barrier cells in low-power or high-efficiency applications. A gate voltage of 5 to 9 V with a drain voltage of 1 to 3 V was employed to program the Schottky barrier cells. Both the non-planar double-gate gate structure and scaled dielectric layers effectively improve the source-side programming. When the gate voltage of 5 V was operated, there were roughly two orders of magnitude greater injected gate currents observed in the ONO-scaled double-gate cells. Five successive programming-trapping iterations were employed to consider the coupling of trapped charges and Schottky barriers, examining the differences in physical mechanisms between different design options. The gate structures, dielectric layers, and gate/drain voltages are key factors in designing transverse scaled Schottky barrier charge-trapping cells for low-power and high-efficiency applications.

【 授权许可】

Unknown