On the Characterization and Separation of Trapping and Ferroelectric Behavior in HfZrO FET

IEEE Journal of the Electron Devices Society

Marc Heyns¹  Md. Nur Kutubul Alam¹  Jan Van Houdt¹  Mihaela Popovici¹  Ben Kaczer¹  Lars-Ake Ragnarsson¹  Naoto Horiguchi¹  Gerhard Rzepa² 

[1] IMEC, Institute for Microelectronics, Leuven, Belgium;Institute for Microelectronics, TU Vienna, Vienna, Austria;

关键词: Steep-slope FET;    ferroelectric FET;    trap characterization;   

DOI  :  10.1109/JEDS.2019.2902953

来源: DOAJ

【 摘 要 】

N-channel FETs with ferroelectric (FE) HfZrO gate oxide are fabricated, showing steep subthreshold slope under certain conditions. Possible origins of I_D-V_G hysteresis, the hysteresis versus subthreshold slope tradeoff, dependence on the bias voltage and temperature and the competition between trapping and FE behavior are reported and discussed. A band of active traps in the FE layer responsible for charge trapping during device operation is characterized. Transient I_D-V_G measurements are introduced to facilitate differentiating between trapping and FE behavior during subthreshold slope measurements.

【 授权许可】

Unknown