An FPGA Implementation of a Convolutional Auto-Encoder

Applied Sciences

Wei Zhao¹  Zuchen Jia¹  Xiaosong Wei¹  Hai Wang² 

[1] Key Laboratory of Electronic Equipment Structure Design, Ministry of Education, Xidian University, Xi’an 710071, China;School of Aerospace Science and Technology, Xidian University, Xi’an 710071, China;

关键词: convolutional auto-encoder;    neural network;    image compression;    FPGA;   

DOI  :  10.3390/app8040504

来源: DOAJ

【 摘 要 】

In order to simplify the hardware design and reduce the resource requirements, this paper proposes a novel implementation of a convolutional auto-encoder (CAE) in a field programmable gate array (FPGA). Instead of the traditional framework realized in a layer-by-layer way, we designed a new periodic layer-multiplexing framework for CAE. Only one layer is introduced and periodically reused to establish the network, which consumes fewer hardware resources. Moreover, by fixing the number of channels, this framework can be applicable to an image of arbitrary size. Furthermore, to effectively improve the speed of convolution calculation, the parallel convolution method is used based on shift registers. Experimental results show that the proposed CAE framework achieves good performance in image compression. It can be observed that our CAE framework has advantages in resources occupation, operation speed, and power consumption, indicating great potential for application in digital signal processing.

【 授权许可】

Unknown