A Low-Dropout Regulator with PSRR Enhancement through Feed-Forward Ripple Cancellation Technique in 65 nm CMOS Process

Electronics

Young-Joe Choe¹  Hyohyun Nam¹  Jung-Dong Park² 

[1] Division of Electronics and Electrical Engineering, Dongguk University, Seoul 04620, Korea;Jung-Dong Park, Division of Electrical and Electronics Engineering, Dongguk University, Seoul 04620, Korea;

关键词: cmos;    ldo;    low dropout;    power supply rejection ratio;    regulation;   

DOI  :  10.3390/electronics9010146

来源: DOAJ

【 摘 要 】

In this paper, a low-dropout (LDO) regulator with an enhanced power supply rejection ratio (PSRR) is proposed with a feed-forward ripple cancellation technique (FFRC) in 65 nm CMOS technology. This technique significantly improves the PSRR over a wide range of frequencies, compared to a conventional LDO regulator. The LDO regulator provides 35−76.8 dB of PSRR in the range of 1 MHz−1 GHz, which shows up to 30 dB of PSRR improvement, compared with that of the conventional LDO regulator. The implemented LDO regulator has a dropout voltage of 0.22 V and a maximum load current of 20 mA. It can also provide an output voltage of 0.98 V at a range of 1−1.3 V of the input voltage. The load regulation is 2.3 mV/mA while the line regulation is 0.05 V/V. The circuit consumes 385 μA with an input voltage of 1.2 V. The total area without pads is 0.092 mm².

【 授权许可】

Unknown