An 8T SRAM Array with Configurable Word Lines for In-Memory Computing Operation

Electronics

Junning Chen¹  Qiang Zhao¹  Chunyu Peng¹  Jin Zhang¹  Wenjuan Lu¹  Zhiting Lin¹  Xiulong Wu¹ 

[1] School of Electronics and Information Engineering, Anhui University, Hefei 230601, China;

关键词: ternary multiplication;    unsigned multibit multiplication;    logic operation;    in-memory computing (IMC);    unidirectional charging and discharging;   

DOI  :  10.3390/electronics10030300

来源: DOAJ

【 摘 要 】

In-memory computing (IMC) has been widely accepted to be an effective method to improve energy efficiency. To realize IMC, operands in static random-access memory (SRAM) are stored in columns, which contradicts SRAM write patterns and requires additional data movement. In this paper, an 8T SRAM array with configurable word lines is proposed, in where the operands are arranged in rows, following the traditional SRAM storage pattern, and therefore additional data movement is not required. The proposed structure supports three different computing modes. In the ternary multiplication mode, the reference voltage generation column is not required. The energy of computing is only 1.273 fJ/bit. In the unsigned multibit multiplication mode, discharge and charging paths are used to enlarge the voltage difference of the least significant bit. In the logic operation mode, different types of operations (e.g., IMP, OR, NOR, XNOR, and XOR) are achieved in a single cycle. The frequency of logic computing is up to 909 MHz.

【 授权许可】

Unknown