Design Space Exploration on High-Order QAM Demodulation Circuits: Algorithms, Arithmetic and Approximation Techniques

Electronics

Vasileios Leon¹  Dimitrios Soudris¹  George Lentaris¹  Ioannis Stratakos¹  Giorgos Armeniakos¹ 

[1] School of Electrical and Computer Engineering, National Technical University of Athens, 15780 Athens, Greece;

关键词: QAM demodulation;    approximate computing;    approximate arithmetic;    FPGA;    design space exploration;    log likelihood ratio;   

DOI  :  10.3390/electronics11010039

来源: DOAJ

【 摘 要 】

Every new generation of wireless communication standard aims to improve the overall performance and quality of service (QoS), compared to the previous generations. Increased data rates, numbers and capabilities of connected devices, new applications, and higher data volume transfers are some of the key parameters that are of interest. To satisfy these increased requirements, the synergy between wireless technologies and optical transport will dominate the 5G network topologies. This work focuses on a fundamental digital function in an orthogonal frequency-division multiplexing (OFDM) baseband transceiver architecture and aims at improving the throughput and circuit complexity of this function. Specifically, we consider the high-order QAM demodulation and apply approximation techniques to achieve our goals. We adopt approximate computing as a design strategy to exploit the error resiliency of the QAM function and deliver significant gains in terms of critical performance metrics. Particularly, we take into consideration and explore four demodulation algorithms and develop accurate floating- and fixed-point circuits in VHDL. In addition, we further explore the effects of introducing approximate arithmetic components. For our test case, we consider 64-QAM demodulators, and the results suggest that the most promising design provides bit error rates (BER) ranging from ${10}^{-1}$ to ${10}^{-4}$ for SNR 0–14 dB in terms of accuracy. Targeting a Xilinx Zynq Ultrascale+ ZCU106 (XCZU7EV) FPGA device, the approximate circuits achieve up to $98\%$ reduction in LUT utilization, compared to the accurate floating-point model of the same algorithm, and up to a $122\%$ increase in operating frequency. In terms of power consumption, our most efficient circuit configurations consume 0.6–1.1 W when operating at their maximum clock frequency. Our results show that if the objective is to achieve high accuracy in terms of BER, the prevailing solution is the approximate LLR algorithm configured with fixed-point arithmetic and 8-bit truncation, providing $81\%$ decrease in LUTs and $13\%$ increase in frequency and sustains a throughput of 323 Msamples/s.

【 授权许可】

Unknown