A Latency-Optimized Network-on-Chip with Rapid Bypass Channels

Micromachines

Wenheng Ma¹  Yudi Gao¹  Ningmei Yu¹  Xiyao Gao¹ 

[1] Faculty of Automation and Information Engineering, Xi’an University of Technology, Xi’an 710048, China;

关键词: network-on-chip;    latency optimization;    bypass channel;    single-cycle multi-hop;   

DOI  :  10.3390/mi12060621

来源: DOAJ

【 摘 要 】

Network-on-Chips with simple topologies are widely used due to their scalability and high bandwidth. The transmission latency increases greatly with the number of on-chip nodes. A NoC, called single-cycle multi-hop asynchronous repeated traversal (SMART), is proposed to solve the problem by bypassing intermediate routers. However, the bypass setup request of SMART requires additional pipeline stages and wires. In this paper, we present a NoC with rapid bypass channels that integrates the bypass information into each flit. In the proposed NoC, all the bypass requests are delivered along with flits at the same time reducing the transmission latency. Besides, the bypass request is unicasted in our design instead of broadcasting in SMART leading to a great reduction in wire overhead. We evaluate the NoC in four synthetic traffic patterns. The result shows that the latency of our proposed NoC is 63.54% less than the 1-cycle NoC. Compared to SMART, more than 80% wire overhead and 27% latency are reduced.

【 授权许可】

Unknown