Material-Device-Circuit Co-Design of 2-D Materials-Based Lateral Tunnel FETs

IEEE Journal of the Electron Devices Society

Iuliana Radu¹  Tarun Agarwal²  Marc Heyns²  Wim Dehaene²  Gianluca Fiori³  Bart Soree⁴ 

[1] di Pisa, Pisa, Italy;Beyond CMOS logic devices, IMEC, Heverlee, Belgium;Dipartimento di Ingegneria dell&x2019;Informazione, Universita&x2019;

关键词: Tunnel FETs;    two-dimensional materials;    energy-delay;    black phosphorus;   

DOI  :  10.1109/JEDS.2018.2827164

来源: DOAJ

【 摘 要 】

In this paper, the 2-D materials-based lateral TFETs are holistically assessed by co-optimizing the material parameters, device designs, and digital circuit figure-of-merits, e.g., energy consumption and delay. Effect of material parameters such as effective mass and bandgap are studied using a two-band quantum simulation approach in the ballistic regime. The selection of 2-D material parameters is discussed from the energy-delay perspective. Single-gate and double-gate 2-D TFETs are compared with the optimum material parameters. Using a simple analytical model for 2-D TFETs, the quantum simulation results for different materials and device designs are analyzed. We show that the gate-to-source fringing fields play a significant role in 2-D TFETs performance. To mitigate the effect of fringing fields on tunneling lengths, an interfacial layer (IL) is introduced between high-κ and 2-D material, resulting a 3-4× increase in ON current. Using circuit-level metrics, we show that a tri-layer black phosphorus (BP) TFET using IL can outperform monolayer BP MOSFETs for the supply voltages below 0.5 V.

【 授权许可】

Unknown