Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application

IEEE Access

Bo Wang¹  Yan Ran¹  Yongkai Li¹  Zhikai Liao¹  Wei Feng¹  Ping Yang¹  Xu Qi¹  Yi Niu¹  Hua Fan²  Wei Li²  Yuanjun Cen²  Hadi Heidari³  Quanyuan Feng⁴ 

[1] Chengdu Sino Microelectronics Technology Company Ltd., Chengdu, China;School of Electronic Science and Engineering, University of Electronic Science and Technology of China, Chengdu, China;School of Engineering, University of Glasgow, Glasgow, U.K;School of Information Science and Technology, Southwest Jiaotong University, Chengdu, China;

关键词: Segmented capacitor array;    SAR ADC;    linearity error;    calibration;   

DOI  :  10.1109/ACCESS.2020.3024807

来源: DOAJ

【 摘 要 】

This paper proposes a 16-bit 6-channel high-voltage successive approximation register (SAR) ADC with an optimized 5 + 5 + 6 segmented capacitor array. The lower 10 bits of the capacitor array are all composed of unit capacitors without any calibration unit. Without calibration, the lower 10 bits of the capacitor array can ensure 10-bit conversion accuracy. Every of the upper 6 bits of the capacitor array contains a linearity calibration unit. The linearity error of the upper 6 bits is calibrated by the linearity calibration unit. The 16-bit is manufactured by a 0.6μm standard COMS process, and the total chip area of 6-channel ADC including pads is 6.6mm × 6.6mm. As for single channel SAR ADC, the area is 0.9mm × 2.0mm. The measurement results show that the effective conversion accuracy of the SAR ADC reaches 13 bits by using novel differential nonlinearity (DNL) and integral nonlinearity (INL) calibration methods. The power is 80mW, corresponding to a Figure of Merit (FOM) of 48 pJ/conv.-step.

【 授权许可】

Unknown