Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology

IEEE Access

Goran Panic¹  Lukasz Lopacinski²  Karthik Krishnegowda²  Mohamed Hussein Eissa²  Alireza Hasani³  Rolf Kraemer³  Miroslav Marinkovic³ 

[1] Arquimea Deutschland GmbH, Frankfurt (Oder), Germany;IHP -Leibniz-Institut f&x00FC;r innovative Mikroelektronik, Frankfurt (Oder), Germany;

关键词: 100 Gbps wireless;    terahertz communication;    Reed-Solomon coding;    data link layer;   

DOI  :  10.1109/ACCESS.2019.2907156

来源: DOAJ

【 摘 要 】

In this paper, we show our 165 Gbps data link layer processor for wireless communication in the terahertz band. The design utilizes interleaved Reed-Solomon codes with dedicated link adaptation, fragmentation, aggregation, and hybrid-automatic-repeat-request. The main advantage is the low-chip area required to fabricate the processor, which is at least two times lower than the area of low-density parity-check decoders. Surprisingly, our solution loses only ~1 dB gain when compared to high-speed low-density parity-check decoders. Moreover, with only 2.38 pJ/bit of energy consumption at 0.8 V, one of the best results in the class of comparable implementations has been achieved. Alongside, we show our vision of a complete 100 Gbps wireless transceiver, including radio frequency frontend and baseband processing. For the baseband realization, we propose a parallel sequence spread spectrum and channel combining at the baseband level. Challenges to high-speed wireless transmission at the terahertz band are addressed as well. To the authors' best knowledge, it is one of the first data link layer implementations that deal with a data rate of ≥ 100 Gbps.

【 授权许可】

Unknown