On the Monte Carlo Matrix Computations on Intel MIC Architecture

Cybernetics and Information Technologies

Alexandrov Vassil¹  Karaivanova Aneta²  Ivanovska Sofiya²  Gurov Todor² 

[1] Barcelona Supercomputing Centre (BSC), Barcelona, Spain, and ICREA – Catallan Institution for Advanced Research Studies, Spain;Institute of Information and Communication Technologies, Bulgarian Academy of Sciences, 1113 Sofia, Bulgaria;

关键词: monte carlo;    matrix computations;    intel mic;    high performance computing (hpc) scalability;   

DOI  :  10.1515/cait-2017-0054

来源: DOAJ

【 摘 要 】

The tightened energy requirements when designing state-of-the-art high performance computing systems lead to the increased use of computational accelerators. Intel introduced the Many Integrated Core (MIC) architecture for their line of accelerators and successfully competes with NVIDIA on basis of price/performance and ease of development. Although some codes may be ported successfully to Intel MIC architecture without significant modifications, in order to achieve optimal performance one has to make the best use of the vector processing capabilities of the architecture. In this work we present our implementation of Quasi-Monte Carlo methods for matrix computations specifically optimised for the Intel Xeon Phi accelerators. To achieve optimal parallel efficiency we make use of both MPI and OpenMP.

【 授权许可】

Unknown