Binary Memory Implemented by Using Variable Gain Amplifiers With Multipliers

IEEE Access

Roman Sotner¹  Jiri Petrzela¹ 

[1] Department of Radio Electronics, SIX Research Center, Brno University of Technology, Brno, Czech Republic;

关键词: Analogue binary memory;    bifurcation diagram;    electronic tuning;    chaos;    Lyapunov exponent;    piecewise-linear (PWL) resistors;   

DOI  :  10.1109/ACCESS.2020.3034665

来源: DOAJ

【 摘 要 】

This work describes design process toward fully analogue binary memory where two coupled piecewise-linear (PWL) resistors are implemented using novel network topology with the voltage gain amplifiers (VGA). These versatile active devices allow slopes of individual segments of ampere-voltage (AV) characteristics associated with PWL two-terminals to be electronically adjustable via the external DC voltage. Numerical analysis of designed binary memory cell covers all mandatory parts: phase portraits, calculation of the largest Lyapunov exponent (LLE), basins of attraction for the typical strange attractors, and high-resolution circuit-oriented bifurcation sequences. A transition from the stable states toward chaotic regime through metastability is proved via real measurement. The robustness of the generated chaotic attractors is verified by captured oscilloscope screenshots.

【 授权许可】

Unknown