IEEE Journal on Exploratory Solid-State Computational Devices and Circuits | |
Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators | |
Rahul Mathur1  Ajay Krishna Ananda Kumar1  Lizy John1  Jaydeep P. Kulkarni1  | |
[1] Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA; | |
关键词: 3-D integration; energy efficient; systolic accelerators; thermal; | |
DOI : 10.1109/JXCDC.2021.3092436 | |
来源: DOAJ |
【 摘 要 】
Machine learning (ML) accelerators have a broad spectrum of use cases that pose different requirements on accelerator design for latency, energy, and area. In the case of systolic array-based ML accelerators, this puts different constraints on processing element (PE) array dimensions and SRAM buffer sizes. The 3-D integration packs more compute or memory in the same 2-D footprint, which can be utilized to build more powerful or energy-efficient accelerators. However, 3-D also expands the design space of ML accelerators by additionally including different possible ways of partitioning the PE array and SRAM buffers among the vertical tiers. Moreover, the partitioning approach may also have different thermal implications. This work provides a systematic framework for performing system-level design space exploration of 3-D systolic accelerators. Using this framework, different 3-D-partitioned accelerator configurations are proposed and evaluated. The 3-D-stacked accelerator designs are modeled using the hybrid wafer bonding technique with a 1.44-
【 授权许可】
Unknown