Design and simulation of high linearity CMOS analog multiplier

Dianzi Jishu Yingyong

Yi Maoxiang¹  Tian Ruizhi¹  Zhang Qingzhe¹  Wang Tao¹  Wang Peng¹  Ding Kun¹ 

[1] National Model Institute of Microelectronics，School of Electronic Science and Applied Physics，Hefei University of Technology， Hefei 230009，China;

关键词: analog multiplier;    cmos gilbert unit;    active attenuator;    high linearity;   

DOI  :  10.16157/j.issn.0258-7998.190954

来源: DOAJ

【 摘 要 】

A high linearity CMOS analog multiplier is designed and simulated. The input signal is preprocessed by active attenuator and the CMOS Gilbert multiplier is used for multiplication of the signal, and the bias circuit is designed meanwhile. When the supply voltage is ±1.8 V and the input range is ±0.6 V, the output range is less than ±25 mV and good linearity of the analog multiplier is obtained using optimized characteristics of transistors. The frequency doubling character of the analog multiplier is favorable since the -3 dB bandwidth of the analog multiplier is 181 MHz. Moreover, the temperature characteristic of multiplier is simulated and the layout of multiplier is designed optimally，and the relationship between linearity and output amplitude is discussed. The linearity of the multiplier during wider input range proposed herein is higher than that in the references.

【 授权许可】

Unknown