Predictive Direct Torque Control Application-Specific Integrated Circuit With a Fuzzy Proportional–Integral–Derivative Controller and a New Round-Off Algorithm

IEEE Access

Chun-Ting Lee¹  Guo-Ming Sung¹  Hsiang-Yuan Hsieh¹  Chong-Cheng Huang¹ 

[1] Electrical Engineering Department, National Taipei University of Technology, Taipei, Taiwan;

关键词: Direct torque control (DTC);    predictive calculation;    fuzzy PID controller;    round-off algorithm;    application-specific integrated circuit (ASIC);    induction motor (IM);   

DOI  :  10.1109/ACCESS.2022.3171861

来源: DOAJ

【 摘 要 】

This study developed a predictive direct torque control (PDTC) application-specific integrated circuit (ASIC) with a fuzzy proportional–integral–derivative (PID) controller and a new round-off calculation circuit for improving the ripple response of a hysteresis controller when sampling and calculating delay times in an induction motor drive. The proposed PDTC ASIC not only calculates the stator’s magnetic flux and torque by detecting three-phase currents, three-phase voltages, and rotor speed but also eliminates large ripples in the torque and flux by using the fuzzy PID controller. Furthermore, the proposed round-off algorithm reduces the calculation error of the composite flux. A fuzzy voltage vector switching table is proposed not only to speed up the calculating speed but also to resolve the instability generated by its large torque and flux ripples. The Verilog hardware description language was used to implement the hardware architecture, and the aforementioned ASIC was fabricated using the 0.18- $\mu \text{m}$ 1P6M CMOS process of the TSMC by employing the cell-based design method. The predictive calculations, fuzzy PID controller, fuzzy voltage vector switching table, and round-off calculation algorithm improved not only the ripple issue faced in traditional direct torque control but also the control stability and robustness. The measurement results indicate that the proposed PDTC ASIC has an operating frequency, a sampling rate, and a dead time of 50 MHz, 100 kS/s, and 100 ns, respectively, at a supply voltage of 1.8 V. The power consumption and chip area of this ASIC are 1.0027 mW and 1.169 $\times $ 1.168 mm², respectively. The main advantages of the proposed PDTC ASIC are its low power consumption, small chip area, robustness, and convenience.

【 授权许可】

Unknown