Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs

IEEE Open Journal of Circuits and Systems

Vincent O'Brien¹  Eric Thompson²  Brendan Mullane³  Shantanu Mehta³  Daniel O'Hare⁴ 

[1] Department of Aerospace, Mechanical and Electronic Engineering, Institute of Technology Carlow, Carlow, Ireland;Department of Desgin, Analog Devices, Limerick, Ireland;Department of Electronic and Computer Engineering, Circuits and Systems Research Centre, University of Limerick, Limerick, Ireland;MCCI, Tyndall National Institute, Cork, Ireland;

关键词: Tri-level;    current-steering;    DACs;    thermal noise;    DNL;    INL;   

DOI  :  10.1109/OJCAS.2020.2994838

来源: DOAJ

【 摘 要 】

This paper presents the design of a low-latency, highly linear current-steering DAC for use in continuous-time ADCs. A detailed analysis of equivalent unary-weighted current-steering DAC topologies in terms of mismatch, noise, and output-impedance related distortion is carried out. From this analysis, we propose a tri-level DAC design that achieves 12-bit static linearity and is suitable for implementation in a continuous-time ADC architecture. To reduce output-impedance related distortion, the design combines DAC slice impedance matching with a proposed compensation technique. By incorporating the tri-level DAC in a continuous-time ADC architecture, the technique demonstrates ~ 8dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.

【 授权许可】

Unknown