Fully Depleted, Trench-Pinned Photo Gate for CMOS Image Sensor Applications

Sensors

Laurent Montes¹  Panagiota Morfouli¹  Guo-Neng Lu²  Catherine Chaton³  Yvon Cazaux³  Jihane Arnaud⁴  Francois Roy⁴  Daniel Benoit⁴  Romain Duru⁴  Andrej Suler⁴  Thomas Dalleau⁴ 

[1] IMEP-LaHC, Université Grenoble Alpes, 38016 Grenoble, France;INL, Université Claude Bernard Lyon 1, 69622 Villeurbanne, France;LETI-CEA Tech, 17 rue des Martyrs, 38054 Grenoble, France;STMicroelectronics, 850 Rue Jean Monnet, 38921 Colles, France;

关键词: cmos image sensor (cis);    pixel;    photo gate;    transfer gate;    capacitive deep trench isolation;    surface passivation;    dark current;   

DOI  :  10.3390/s20030727

来源: DOAJ

【 摘 要 】

Tackling issues of implantation-caused defects and contamination, this paper presents a new complementary metal−oxide−semiconductor (CMOS) image sensor (CIS) pixel design concept based on a native epitaxial layer for photon detection, charge storage, and charge transfer to the sensing node. To prove this concept, a backside illumination (BSI), p-type, 2-µm-pitch pixel was designed. It integrates a vertical pinned photo gate (PPG), a buried vertical transfer gate (TG), sidewall capacitive deep trench isolation (CDTI), and backside oxide−nitride−oxide (ONO) stack. The designed pixel was fabricated with variations of key parameters for optimization. Testing results showed the following achievements: 13,000 h+ full-well capacity with no lag for charge transfer, 80% quantum efficiency (QE) at 550-nm wavelength, 5 h+/s dark current at 60 °C, 2 h+ temporal noise floor, and 75 dB dynamic range. In comparison with conventional pixel design, the proposed concept could improve CIS performance.

【 授权许可】

Unknown