Balancing the Leakage Currents in Nanometer CMOS Logic—A Challenging Goal

Applied Sciences

Bijan Fadaeinia¹  Thorben Moos¹  Amir Moradi¹ 

[1] Horst Görtz Institute for IT-Security, Ruhr University Bochum, 44801 Bochum, Germany;

关键词: side-channel analysis;    static power consumption;    current leakage;    hiding;   

DOI  :  10.3390/app11157143

来源: DOAJ

【 摘 要 】

The imbalance of the currents leaked by CMOS standard cells when different logic values are applied to their inputs can be exploited as a side channel to recover the secrets of cryptographic implementations. Traditional side-channel countermeasures, primarily designed to thwart the dynamic leakage behavior, were shown to be much less powerful against this static threat. Thus, a special protection mechanism called Balanced Static Power Logic (BSPL) has been proposed very recently. Essentially, fundamental standard cells are re-designed to balance their drain-source leakage current independent of the given input. In this work, we analyze the BSPL concept in more detail and reveal several design issues that limit its effectiveness as a universal logic library. Although balancing drain-source currents remains a valid approach even in more advanced technology generations, we show that it is conceptually insufficient to achieve a fully data-independent leakage behavior in smaller geometries. Instead, we suggest an alternative approach, so-called improved BSPL (iBSPL). To evaluate the proposed method, we use information theoretic analysis. As an attack strategy, we have chosen Moments-Correlating DPA (MCDPA), since this analysis technique does not depend on a particular leakage model and allows a fair comparison. Through these evaluation methods, we show iBSPL demands fewer resources and delivers better balance in the ideal case as well as in the presence of process variations.

【 授权许可】

Unknown