Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays

Sensors

Santiago Celma¹  Carlos Sánchez-Azqueta²  Bernhard Goll²  Horst Zimmermann² 

[1] Group of Electronic Design, Aragón Institute of Engineering Research, Universidad de Zaragoza, Pedro Cerbuna 12, Zaragoza 50009, Spain;Institute of Electrodynamics, Microwave and Circuit Engineering, Vienna University of Technology, Gußhausstraße 25/354, Vienna 1040, Austria;

关键词: integrated optoelectronics;    integrated pin photodiode;    integrating receiver;   

DOI  :  10.3390/s16060761

来源: DOAJ

【 摘 要 】

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of −26.0 dBm and −25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10−9 ) with an energy efficiency of 2 pJ/bit.

【 授权许可】

Unknown