Modelling and analysis of half‐/full‐bridge hybrid MMC when riding through DC‐side pole‐to‐ground fault

High Voltage

Pingliang Zeng¹  Zhen He¹  Jiabing Hu²  Lei Lin² 

[1] School of Automation Hangzhou Dianzi University Hangzhou China;State Key Laboratory of Advanced Electromagnetic Engineering and Technology School of Electrical and Electronic Engineering Huazhong University of Science and Technology Wuhan China;

DOI  :  10.1049/hve2.12144

来源: DOAJ

【 摘 要 】

Abstract In a modular multilevel converter‐based high‐voltage direct current (MMC‐HVDC) system, the dc fault ride through (FRT) control is an effective way to deal with a dc‐side pole‐to‐ground (PTG) fault. However, the setting of FRT duration brings potential hazards: 1) MMC will face the risk of “secondary short circuit” if FRT duration is short; 2) ac grid may have power angle stability issue if FRT duration is long. To avoid these hazards and provide theoretical guidance for the FRT duration setting, transient behaviour of dc fault current during the PTG FRT stage is explored in this work. Firstly, challenges of the transient analysis are summarised as non‐linearity and high‐order issues. In light of this, numerical and Hilbert‐Huang Transformation methods are introduced to evaluate the non‐linearity issue. It is found that the path of MMC from dc current to dc internal voltage is weakly non‐linear. Hence, a linear transient model is built to analyse the dc fault current. By participation factor analysis, the order of the proposed model is further reduced, so that an analytical expression of the dc fault current is approximately derived. Based on the analytical expression, regularities and mechanism of dc fault current are fully revealed. Application of the transient analysis to the setting of FRT duration is elaborated in detail. Finally, the PSCAD/EMTDC simulation verifies the validity of the proposed model and analytical expression.

【 授权许可】

Unknown