Implementation of NoC on FPGA with Area and Power Optimization

EAI Endorsed Transactions on Context-aware Systems and Applications

Huma Urooj¹  Muhammad Sethi¹  Momil Ijaz¹ 

[1] Department of Computer Systems Engineering, University of Engineering and Technology, Peshawar, Pakistan;

关键词: Network on chip;    node;    switching;    packet;    crossbar;   

DOI  :  10.4108/eai.23-5-2019.158953

来源: DOAJ

【 摘 要 】

On-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems,size, speed, power and area. The goal of working was to design a usable and researchable general-purpose 2x2 mesh NoC architecture, which is not application specific, and have optimized area and power. Desired NoC was coded and deployed on FPGA Spartan-3 kit in a generic mode, with the efficient area and power utilization than traditional deployments.

【 授权许可】

Unknown