Hardware RTOS: Custom Scheduler Implementation Based on Multiple Pipeline Registers and MIPS32 Architecture

Electronics

Ionel Zagan¹  VasileGheorghiță Găitan¹ 

[1] Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University, 720229 Suceava, Romania;

关键词: FPGA;    operating system;    real-time systems;    task scheduling;   

DOI  :  10.3390/electronics8020211

来源: DOAJ

【 摘 要 】

The task context switch operation, the inter-task synchronization and communication mechanisms, as well as the jitter occurred in treating aperiodic events, are crucial factors in implementing real-time operating systems (RTOS). In practice and literature, several solutions can be identified for improving the response speed and performance of real-time systems. Software implementations of RTOS-specific functions can generate significant delays, adversely affecting the deadlines required for certain applications. This paper presents an original implementation of a dedicated processor, based on multiple pipeline registers, and a hardware support for a dynamic scheduler with the following characteristics: performs unitary event management, provides access to architecture shared resources, prioritizes and executes the multiple events expected by the same task. The paper also presents a method through which interrupts are assigned to tasks. Through dedicated instructions, the integrated hardware scheduler implements tasks synchronization with multiple prioritized events, thus ensuring an efficient functioning of the processor in the context of real-time control.

【 授权许可】

Unknown