New Heuristic Algorithm for Low Energy Mapping for 2.5-D Integration

Electronics

卷:11

Xinwei Peng¹  Jicong Zhao¹  Haiyan Sun¹  Dongqing Cang¹  Yanhua Liu¹ 

[1] School of Electrical Engineering, Nantong University, Nantong 226019, China;

关键词: 2.5-D IC;    chiplet placement;    low communication consumption;    secondary local exploration;   

DOI  :  10.3390/electronics11121817

来源: DOAJ

【 摘 要 】

A chiplet placement algorithm for 2.5-D IC integration on an interposer is discussed in this paper. Inspired by the NoC (network-on-chip) mapping problem, we propose a novel chiplet placement algorithm called the CCEOA (chiplet communication energy optimization algorithm), which takes into account the actual size of the chiplet. The CCEOA can map chiplets to mesh topology, resulting in a layout with a low CEC (communication energy consumption). The algorithm considers the spacing of the chiplets while selecting the initial nodes and the nodes to map the next chiplet. Furthermore, because there exist nodes resulting in the same CEC increment during the mapping process, the algorithm adopts a secondary local exploration strategy to further select nodes. Meanwhile, the lateral and vertical placements of chiplets are also considered. The algorithm is implemented and evaluated with a 2.5-D IC integration with 22 chiplets to demonstrate its efficiency and the accuracy.

【 授权许可】

Unknown