From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits

Electronics

卷:11

Lionel Trojman¹  Eduardo Holguin¹  Luis-Miguel Procel²  Marco Villegas²  Ramiro Taco² 

[1] Institut Supérieur Electronique de Paris (Isep), LISITE, 10 rue de Vanves, 92130 Issy-les-Moulineaux, France;

[2] Instituto de Micro y Nanoelectrónica (IMNE), Universidad San Francisco de Quito, Quito 170901, Ecuador;

关键词: TFET;    32 nm;    multiplier;    full wave rectifier;    CCDD;    PCE;   

DOI  :  10.3390/electronics11040525

来源: DOAJ

【 摘 要 】

In this present work, different Cross-Coupled Differential Drive (CCDD) CMOS bridge rectifiers are designed using either 32 nm or Tunnel-FET (TFET) technology. Commercial PDK has been used for the 32 nm technology, while lookup tables (LUT) resulting from a physics model have been applied for the TFET. To consider the parasitic effects for the circuit performances, the 32 nm-based circuits have been laid out, while a parasitic model has been included in the TFET LUT for circuit implementation. In this work, the post-layout simulations, including parasitic, demonstrate for conventional CCDD circuits that TFET technology has a larger dynamic range (DR) (>60%) and better 1 V-sensitivity than the 32 nm planar technology has. Note that, in this case, the figure of merit defined by the Voltage Conversion Efficiency (VCE) and Power Conversion Efficiency (PCE) remains somewhat similar. On the other hand, topology proposing better VCE at the cost of low PCE shows lower performance than expected in 32 nm than in reported data for larger technology nodes (e.g., 180 nm). The TFET-based circuit shows a PCE of 70%, VCE of 82% with an 8 dB DR (>60%), and the best 1 V-sensitivity in this work. Because of the low-bias condition and the good reverse current blocking (unidirectional channel), the TFET offers new perspectives for RF-DC rectifier/multiplier topology, which are usually limited with planar technology.

【 授权许可】

Unknown