Superjunction LDMOS With Dual Gate for Low On-Resistance and High Transconductance

IEEE Journal of the Electron Devices Society

卷:8

Zhen Cao¹  Licheng Jiao² 

[1] Key Laboratory of Intelligent Perception and Image Understanding of Ministry of Education, International Research Center for Intelligent Perception and Computation, Joint International Research Laboratory of Intelligent Perception and Computation, School of Artificial Intelligence, Xidian University, Xi&x2019;

[2] an, China;

关键词: Superjunction MOSFET;    N-buffer;    trench gate;    breakdown voltage;    ON-resistance;   

DOI  :  10.1109/JEDS.2020.3011929

来源: DOAJ

【 摘 要 】

In this paper, a novel bulk silicon lateral superjunction double diffused MOSFET (SJ-LDMOS) with dual gate (DG) is proposed and its mechanism is investigated by numerical TCAD simulations. The proposed structure features the combination of a trench gate and a planar gate, forming two current conduction paths. One current conduction takes place along the highly doped N-pillar. The other is through the N-buffer layer ensuring uniform current distributions, which solves the problem of low conduction in the N-buffer layer of the SJ-LDMOS structures. The dual conduction paths improve the current uniformity through the entire SJ layer and the N-buffer layer, which effectively reduces the resistance of the device. Simulation results indicate that the proposed device is predicted to achieve a high breakdown voltage (BV) of 643 V and an extremely low specific ON-resistance (R_ON,sp) of 28.53 mΩ·cm², which is by 46.7 % lower than that of the previously N-buffer SJ-LDMOS structures with the same drift length. Besides, the transconductance of DG SJ-LDMOS is increased by 54.5 % and the figure of merit (FOM) on BV²/R_ON,sp of DG SJ-LDMOS is increased by 85.5 %.

【 授权许可】

Unknown