Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits

IEEE Access

卷:8

Muhammad Imran¹  Jooho Kim¹  Jaeyong Chung²  Taehyun Kwon³  Joon-Sung Yang⁴  Hyunseung Han⁵ 

[1] Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South Korea;

[2] Department of Electronics Engineering, Incheon National University, Incheon, South Korea;

[3] Department of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon, South Korea;

[4] Department of Systems Semiconductor Engineering, Yonsei University, Seoul, South Korea;

[5] Memory Division, Samsung Electronics, Hwaseong, South Korea;

关键词: 3-D integrated circuit;    eye diagram simulations;    multiple bits transmission;    through silicon via (TSV);    TSV Virtualization;    TSV repair;   

DOI  :  10.1109/ACCESS.2019.2940211

来源: DOAJ

【 摘 要 】

Three-dimensional (3-D) integration offers a promising solution to the technology scaling barriers. Reliability of the 3-D Integrated Circuits (ICs) is highly dependent on the integrity of the underlying interconnect. Through Silicon Via (TSV) based 3-D ICs would suffer from low yield due to the faults in TSVs. In addition, TSVs introduce stress and noise in the substrate. Adding redundant TSVs for repairing the faulty ones has commonly been proposed to improve the yield of TSV-based 3-D ICs. The existing TSV repair approaches employ a number of spare TSVs in a group of signal TSVs. We propose a TSV virtualization based repair architecture which utilizes a single redundant TSV to repair multiple faulty TSVs. The proposed architecture relies on transmitting multiple bits through a single TSV using multi-level voltage quantization. It makes efficient use of the TSV redundancies in repairing the faulty TSVs. With less number of spare TSVs, the proposed architecture can reduce the area overhead by more than 70%. Reduction in the TSV count allows greater interconnect density and helps to mitigate the TSV-induced noise and stresses. Alternatively, for a similar number of spare TSVs, the proposed method can enhance the fault tolerance capability of the conventional approaches thus leading to an enhanced chip yield. The eye diagram simulations using an electrical model of the TSV show a reduction of less than 5% in noise margin when using a 16-level voltage quantization at a data rate of 5 Gbps which is typical for 3-D integration applications.

【 授权许可】

Unknown