A Power-Efficient Optimizing Framework FPGA Accelerator Based on Winograd for YOLO

IEEE Access

卷:8

Chongchong Yu¹  Chun Bao¹  Le Chang¹  Tao Xie¹  Wenbin Feng² 

[1] School of Computer and Information Engineering, Beijing Technology and Business University, Beijing, China;

[2] State Key Laboratory of Coal Mine Safety Technology, Fushun, China;

关键词: FPGA;    deep learning;    Winograd;    YOLO;    buffer pipeline;   

DOI  :  10.1109/ACCESS.2020.2995330

来源: DOAJ

【 摘 要 】

Accelerating deep learning networks in edge computing based on power-efficient and highly parallel FPGA platforms is an important goal. Combined with deep learning theory, an accelerator design method based on the Winograd algorithm for the deep learning object detection model YOLO under the PYNQ architecture is proposed. A Zynq FPGA is used to build the hardware acceleration platform of a YOLO network. The Winograd algorithm is used to improve traditional convolution. In the FPGA, the numerous multiplication operations in the YOLO network are converted into addition operations, reducing the computational complexity of the model. The data of the original model are processed at a low fixed point, reducing the resource consumption of the FPGA. To optimize memory, a buffer pipeline method is proposed, which further improves the efficiency of the designed accelerator. Experiments show that compared with the acceleration of the YOLO model based on GPUs and other FPGA platforms, the proposed method not only optimizes FPGA resource usage but also reduces power consumption to 2.7 W. Additionally, the detection accuracy loss is less than 3%.

【 授权许可】

Unknown