Layered CMOS SPADs for Low Noise Detection of Charged Particles

Frontiers in Physics

Gianmaria Collazuol¹  Carla Vacchi²  Lodovico Ratti²  Gianmarco Torilla²  Pier Simone Marrocchesi³  Arta Sulay³  Paolo Brogi³  Gian-Franco Dalla Betta⁴  Lucio Pancheri⁴ 

[1] Padova, Italy;Padova, Italy;Pavia, Italy;Pavia, Italy;Siena, Italy;Pisa, Italy;Trento, Italy;Trento, Italy;

关键词: SPAD;    CMOS;    DCR;    charged particle detection;    dual layer;   

DOI  :  10.3389/fphy.2020.607319

来源: Frontiers

【 摘 要 】

This paper reports the characterization of SPAD arrays fabricated in a 150 nm CMOS technology in view of applications to the detection of charged particles. The test vehicle contains SPADs with different active area and operated with different quenching techniques, either passive or active. The set of devices under test (DUTs) consists of single-tier chips, about 30 mm2 in area, with dual-tier structures where two chips are face-to-face bump bonded to each other. In the dual-layer structure obtained in this way, the coincidence signal between overlapping SPAD pairs is read out, with a beneficial impact on the dark count noise performance. The DUT characterization was mainly focused on studying the breakdown voltage in the single-layer arrays and the dark count rate (DCR), measured in different working conditions, in both the single- and the dual-layer structures. Comparison between the DCR performance of the two configurations clearly emphasizes the advantage of the coincidence readout architecture.

【 授权许可】

CC BY