A Low-Power Single-Bit Continuous-Time ΔΣ Converter with 92.5 dB Dynamic Range for Biomedical Applications

Journal of Low Power Electronics and Applications

Sakkarapani Balagopal¹ 

关键词: analog-to-digital converter (ADC);    continuous-time delta-sigma;    data converter;    oversampling;    delta-sigma modulation;    low-pass filter;    low-power design;    low-voltage design;   

DOI  :  10.3390/jlpea2030197

来源: mdpi

【 摘 要 】

A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15 µm FDSOI CMOS process. The overall power efficiency is attained by employing a single-bit ΔΣ and a subthreshold FDSOI process. The loop-filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110 µW power from a 1.5 V power supply when clocked at 6.144 MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) for the third-order, single-bit CT-ΔΣ modulator is 0.271 pJ/level.

【 授权许可】

CC BY   
© 2012 by the authors; licensee MDPI, Basel, Switzerland.