Design of a Parallel Sampling Encoder for Analog to Information (A2I) Converters: Theory, Architecture and CMOS Implementation

Electronics

Thomas S. Murray¹  Philippe O. Pouliquen¹ 

[1] Electrical and Computer Engineering Department, The Johns Hopkins University, Baltimore, MD 21218, USA;

关键词: analog to information converter;    sub-Nyquist sampling;    compressive sensing;    parallel ADCs;   

DOI  :  10.3390/electronics2010057

来源: mdpi

【 摘 要 】

We discuss the architecture and design of parallel sampling front ends for analog to information (A2I) converters. As a way of example, we detail the design of a custom 0.5CMOS implementation of a mixed signal parallel sampling encoder architecture. The system consists of configurable parallel analog processing channels, whose output is sampled by traditional analog-to-digital converters (ADCs). The analog front-end modulates the signal of interest with a high-speed digital chipping sequence and integrates the result prior to sampling at a low rate. An FPGA is employed to generate the chipping sequences and process the digitized samples.

【 授权许可】

CC BY   
© 2013 by the authors; licensee MDPI, Basel, Switzerland.