Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference

Sensors

El Hafed Boufouss¹  Laurent A. Francis²  Valeriya Kilchytska²  Pierre Gérard²  Pascal Simon² 

[1] ICTEAM Institute—Electrical Engineering, Université catholique de Louvain, Maxwell Building, Place du Levant 3, B-1348 Louvain-la-Neuve, Belgium;

关键词: biomedical;    high temperature;    CMOS subthreshold regime;    total ionized dose;    ultra-low power;    voltage reference;   

DOI  :  10.3390/s131217265

来源: mdpi

【 摘 要 】

This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of −40–200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage V_REF depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of V_REF and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm².

【 授权许可】

CC BY   
© 2013 by the authors; licensee MDPI, Basel, Switzerland.