A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme

Materials

Ching-Lin Fan²  Ming-Chi Shang²  Bo-Jyun Li²  Yu-Zuo Lin¹  Shea-Jue Wang³ 

[1] Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei City 106, Taiwan; E-Mail:;Graduate Institute of Electro-Optical Engineering, National Taiwan University of Science and Technology, Taipei City 106, Taiwan; E-Mails:;Institute of Materials Science and Engineering, National Taipei University of Technology, Taipei City 106, Taiwan; E-Mail:

关键词: amorphous indium–gallium–zinc–oxide (a-IGZO);    back-side exposure;    self-aligned process;    thin-film transistor (TFT);    two-photo-mask process;    backside-lift-off (BLO);   

DOI  :  10.3390/ma7085761

来源: mdpi

【 摘 要 】

Minimizing the parasitic capacitance and the number of photo-masks can improve operational speed and reduce fabrication costs. Therefore, in this study, a new two-photo-mask process is proposed that exhibits a self-aligned structure without an etching-stop layer. Combining the backside-ultraviolet (BUV) exposure and backside-lift-off (BLO) schemes can not only prevent the damage when etching the source/drain (S/D) electrodes but also reduce the number of photo-masks required during fabrication and minimize the parasitic capacitance with the decreasing of gate overlap length at same time. Compared with traditional fabrication processes, the proposed process yields that thin-film transistors (TFTs) exhibit comparable field-effect mobility (9.5 cm²/V·s), threshold voltage (3.39 V), and subthreshold swing (0.3 V/decade). The delay time of an inverter fabricated using the proposed process was considerably decreased.

【 授权许可】

CC BY   
© 2014 by the authors; licensee MDPI, Basel, Switzerland.