A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention †

Journal of Low Power Electronics and Applications

Markus Hiienkari³  Jukka Teittinen³  Lauri Koskinen³  Matthew Turnquist²  Jani Mäkipää⁵  Arto Rantala⁵  Matti Sopanen⁵  Mikko Kaltiokallio⁴  David Bol¹ 

[1] Technology Research Center, University of Turku, Joukahaisenkatu 1C, 20520 Turku, Finland;;Department of Micro and Nanosciences, Aalto University, Otakaari 5A, 02150 Espoo, Finland; E-Mail:;Technology Research Center, University of Turku, Joukahaisenkatu 1C, 20520 Turku, Finland; E-Mails:;TDK, Keilaranta 8, 02601 Espoo, Finland; E-Mail:;VTT Technical Research Centre of Finland, Tietotie 3, 02150 Espoo, Finland; E-Mails:

关键词: timing-error prevention (TEP);    Ultra-Low Power (ULP);    digital CMOS;    clock stretching;    near-threshold;    variability;    energy-efficiency;   

DOI  :  10.3390/jlpea5020057

来源: mdpi

【 摘 要 】

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing.

【 授权许可】

CC BY   
© 2015 by the authors; licensee MDPI, Basel, Switzerland.