A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction

Sensors

Guangli Jiang²  Leibo Liu¹  Wenping Zhu²  Shouyi Yin²  Shaojun Wei² 

[1] Institute of Microelectronics, Tsinghua University, Beijing 100084, China;

关键词: AKAZE;    binary feature descriptor;    feature extraction;    hardware architecture;    VLSI implementation;   

DOI  :  10.3390/s150922509

来源: mdpi

【 摘 要 】

This paper proposes a real-time feature extraction VLSI architecture for high-resolution images based on the accelerated KAZE algorithm. Firstly, a new system architecture is proposed. It increases the system throughput, provides flexibility in image resolution, and offers trade-offs between speed and scaling robustness. The architecture consists of a two-dimensional pipeline array that fully utilizes computational similarities in octaves. Secondly, a substructure (block-serial discrete-time cellular neural network) that can realize a nonlinear filter is proposed. This structure decreases the memory demand through the removal of data dependency. Thirdly, a hardware-friendly descriptor is introduced in order to overcome the hardware design bottleneck through the polar sample pattern; a simplified method to realize rotation invariance is also presented. Finally, the proposed architecture is designed in TSMC 65 nm CMOS technology. The experimental results show a performance of 127 fps in full HD resolution at 200 MHz frequency. The peak performance reaches 181 GOPS and the throughput is double the speed of other state-of-the-art architectures.

【 授权许可】

CC BY   
© 2015 by the authors; licensee MDPI, Basel, Switzerland.