Delay Insensitive Ternary CMOS Logic for Secure Hardware

Journal of Low Power Electronics and Applications

Ravi S. P. Nair¹  Scott C. Smith³  Jia Di² 

[1] University of Arkansas, Fayetteville, AR 72701, USA; E-Mail:;Computer Science & Computer Engineering at University of Arkansas, Fayetteville, AR 72701, USA;Electrical and Computer Engineering at North Dakota State University, Fargo, ND 58108, USA; E-Mail:

关键词: Asynchronous Logic;    Delay Insensitive Logic;    Ternary Logic;    Digital Design;    NCL;    Secure Circuits;   

DOI  :  10.3390/jlpea5030183

来源: mdpi

【 摘 要 】

As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI). This paper develops the Delay-Insensitive Ternary Logic (DITL) asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme. DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB) and NULL Convention Logic (NCL) on which it is based. An application of DITL is discussed in designing secure digital circuits resistant to side channel attacks based on measurement of timing, power, and EMI signatures. A Secure DITL Adder circuit is designed at the transistor level, and several variance parameters are measured to validate the efficiency of DITL in resisting side channel attacks. The DITL design methodology is then applied to design a secure 8051 ALU.

【 授权许可】

CC BY   
© 2015 by the authors; licensee MDPI, Basel, Switzerland.