Synthesis Optimization on Galois-Field Based Arithmetic Operators for Rijndael Cipher

Journal of ICT Research and Applications

Petrus Mursanto¹ 

关键词: Galois Field;    Reed Solomon Codec;    VHDL;    FPGA.;   

DOI  :  10.5614/itbj.ict.2011.5.2.2

学科分类：电子、光学、磁材料

来源: Institute for Research and Community Services ITB

【 摘 要 】

A series of experiments has been conducted to show that FPGA synthesis of Galois-Field (GF) based arithmetic operators can be optimized automatically to improve Rijndael Cipher throughput. Moreover, it has been demonstrated that efficiency improvement in GF operators does not directly correspond to the system performance at application level. The experiments were motivated by so many research works that focused on improving performance of GF operators. Each of the variants has the most efficient form in either time (fastest) or space (smallest occupied area) when implemented in FPGA chips. In fact, GF operators are not utilized individually, but rather integrated one to the others to implement algorithms. Contribution of this paper is to raise issue on GF-based application performance and suggest alternative aspects that potentially affect it. Instead of focusing on GF operator efficiency, system characteristics are worth considered in optimizing application performance.

【 授权许可】

Unknown