Design and Evaluation of an Input Buffered Packet Switch

International Arab Journal of Information Technology (IAJIT)

Maryam Madani¹  Shadpour Mallakpour² 

[1] Department of Chemistry, Isfahan University of Technology, Isfahan 84156-83111, I. R. Iran$$Department of Chemistry, Isfahan University of Technology, Isfahan 84156-83111, I. R. IranDepartment of Chemistry, Isfahan University of Technology, Isfahan 84156-83111, I. R. Iran$$;Department of Chemistry, Isfahan University of Technology, Isfahan 84156-83111, I. R. Iran$$Nanotechnology and Advanced Materials Institute, Isfahan University of Technology, Isfahan 84156-83111, I. R. Iran$$Department of Chemistry, Isfahan University of Technology, Isfahan 84156-83111, I. R. IranDepartment of Chemistry, Isfahan University of Technology, Isfahan 84156-83111, I. R. Iran$$Nanotechnology and Advanced Materials Institute, Isfahan University of Technology, Isfahan 84156-83111, I. R. Iran$$Nanotechnology and Advanced Materials Institute, Isfahan University of Technology, Isfahan 84156-83111, I. R. IranDepartment of Chemistry, Isfahan University of Technology, Isfahan 84156-83111, I. R. Iran$$Nanotechnology and Advanced Materials Institute, Isfahan University of Technology, Isfahan 84156-83111, I. R. Iran$$

关键词: Routing;    switch;    multistage interconnection network;    Benes network;    self routing;    VHDL.;   

DOI  :  

学科分类：计算机科学（综合）

来源: Zarqa University

【 摘 要 】

Many architectures of internet routers, ATM and ethernet switches have been proposed and analysed in literature. Theoretically reliable and valid solutions have been developed to achieve high performances but a lot of them are not feasible in practice for commercial and technological reasons. Few papers develop the implementation and simulation aspects. The objective of this paper is the design of a packet switch with a minimum cost and hardware complexity. We propose an input-queuing architecture using a multistage interconnection network and a simple cell selection policy implemented by hardware. The switch is described and simulated using a VHDL language. Performances in terms of throughput and cell loss are evaluated. Keywords: Routing, switch, multistage interconnection network, Benes network, self routing, VHDL.Received June 23, 2004; accepted October 30, 2004Full Text

【 授权许可】

Unknown